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rev. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adg758/adg759 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: ? analog devices, inc., 3 , 4-/8-channel multiplexers in chip scale package functional block diagrams s1 s8 a0 d a1 a2 adg758 s1a a0 da s4a s1b s4b db en adg759 1 of 4 decoder en 1 of 8 decoder a1 features 1.8 v to 5.5 v single supply 2.5 v dual supply 3 on resistance 0.75 on resistance flatness 100 pa leakage currents 14 ns switching times single 8-to-1 multiplexer adg758 differential 4-to-1 multiplexer adg759 20-lead 4 mm 4 mm chip scale package low power consumption ttl-/cmos-compatible inputs for functionally equivalent devices in 16-lead tssop package, see adg708/adg709 applications data acquisition systems communication systems relay replacement audio and video switching battery-powered systems general description the adg758 and adg759 are low voltage, cmos analog m ultiplexers comprising eight single channels and four differential c hannels, respectively. the adg758 switches one of eight inputs (s1?8) to a com mon output, d, as determined by the 3-bit binary address lines a0, a1, and a2. the adg759 switches one of fo ur differential inputs to a common differential output as determined by the 2-bit binary address lines a0 and a1. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. low power consumption and an operating supply range of 1.8 v to 5.5 v make the adg758 and adg759 ideal for battery-powered, portable ins truments. all channels exhibit break-before-make switching action preventing moment ary shorting when switch- ing channels. these switches are designed on an enhanced submicron process t hat provides low power dissipation yet gives high switching speed, very low on resistance and leakage currents. on resistance is in the region of a few ohms and is closely matched between switches and very flat over the full signal range. these parts can operate equally well as either multiplexers or demultiplexers and have an input signal range that extends to the supplies. th e adg758 and adg759 are available in 20-lead chip scale packages. product highlights 1. small 20-lead 4 mm 4 mm chip scale packages (csp). 2. single/dual supply operation. the adg758 and adg759 are fully speci?d and guaranteed with 3 v and 5 v single- supply and 2.5 v dual-supply rails. 3. low r on (3 ? typical). 4. low power consumption (<0.01 w). 5. guaranteed break-before-make switching action. b 2013 781/461-3113
C2C rev. adg758/adg759?pecifications 1 (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) b version ?0 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )3 ? typ v s = 0 v to v dd , i ds = 10 ma; 4.5 5 ? max test circuit 1 on resistance match between 0.4 ? typ channels ( ? r on ) 0.8 ? max v s = 0 v to v dd , i ds = 10 ma on resistance flatness (r flat(on) )0.75 ? typ v s = 0 v to v dd , i ds = 10 ma 1.2 ? max leakage currents v dd = 5.5 v source off leakage i s (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.3 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v d = 4.5 v/1 v, v s = 1 v/4.5 v; 0.1 0.75 na max test circuit 3 channel on leakage i d , i s ( on) 0.01 na typ v d = v s = 1 v, or 4.5 v, test circuit 4 0.1 0.75 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 pf typ dynamic characteristics 2 t transition 14 ns typ r l = 300 ? , c l = 35 pf; test circuit 5 25 ns max v s1 = 3 v/0 v, v s8 = 0 v/3 v break-before-make time delay, t d 8 ns typ r l = 300 ? , c l = 35 pf 1 ns min v s = 3 v; test circuit 6 t on (en) 14 ns typ r l = 300 ? , c l = 35 pf 25 ns max v s = 3 v; test circuit 7 t off (en) 7 ns typ r l = 300 ? , c l = 35 pf 12 ns max v s = 3 v; test circuit 7 charge injection 3pc typ v s = 2.5 v, r s = 0 ? , c l = 1 nf; test circuit 8 off isolation ?0 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz ?0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 channel-to-channel crosstalk ?0 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz ?0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 10 ? db bandwidth 55 mhz typ r l = 50 ? , c l = 5 pf; test circuit 11 c s (off) 13 pf typ f = 1 mhz c d (off) adg758 85 pf typ f = 1 mhz adg759 42 pf typ f = 1 mhz c d , c s (on) adg758 96 pf typ f = 1 mhz adg759 48 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.001 a typ digital inputs = 0 v or 5.5 v 1.0 a max notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. speci?ations subject to change without notice. b
C3C rev. adg758/adg759 specifications 1 (v dd = 3 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) b version ?0 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance (r on )8 ? typ v s = 0 v to v dd , i ds = 10 ma; 11 12 ? max test circuit 1 on resistance match between 0.4 ? typ v s = 0 v to v dd , i ds = 10 ma channels ( ? r on ) 1.2 ? max leakage currents v dd = 3.3 v source off leakage i s (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.3 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v s = 3 v/1 v, v d = 1 v/3 v; 0.1 0.75 na max test circuit 3 channel on leakage i d , i s ( on) 0.01 na typ v s = v d = 1 v or 3 v; test circuit 4 0.1 0.75 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 pf typ d ynamic characteristics 2 t transition 18 ns typ r l = 300 ? , c l = 35 pf; test circuit 5 30 ns max v s1 = 2 v/0 v, v s2 = 0 v/2 v break-before-make time delay, t d 8 ns typ r l = 300 ? , c l = 35 pf 1 ns min v s = 2 v; test circuit 6 t on (en) 18 ns typ r l = 300 ? , c l = 35 pf 30 ns max v s = 2 v; test circuit 7 t off (en) 8 ns typ r l = 300 ? , c l = 35 pf 15 ns max v s = 2 v; test circuit 7 charge injection 3pc typ v s = 1.5 v, r s = 0 ? , c l = 1 nf; test circuit 8 off isolation ?0 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz ?0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 channel-to-channel crosstalk ?0 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz ?0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 10 ? db bandwidth 55 mhz typ r l = 50 ? , c l = 5 pf; test circuit 11 c s (off) 13 pf typ f = 1 mhz c d (off) adg758 85 pf typ f = 1 mhz adg759 42 pf typ f = 1 mhz c d , c s (on) adg758 96 pf typ f = 1 mhz adg759 48 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 0.001 a typ digital inputs = 0 v or 3.3 v 1.0 a max notes 1 temperature ranges are as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. speci?ations subject to change without notice. b
C4C rev. adg758/adg759?pecifications 1 dual supply b version ?0 c parameter +25 c to +85 c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 2.5 ? typ v s = v ss to v dd , i ds = 10 ma; 4.5 5 ? max test circuit 1 on resistance match between 0.4 ? typ channels ( ? r on ) 0.8 ? max v s = v ss to v dd , i ds = 10 ma on resistance flatness (r flat(on) ) 0.6 ? typ v s = v ss to v dd , i ds = 10 ma 1.0 ? max leakage currents v dd = +2.75 v, v ss = ?.75 v source off leakage i s (off) 0.01 na typ v s = +2.25 v/?.25 v, v d = ?.25 v/+2.25 v; 0.1 0.3 na max test circuit 2 drain off leakage i d (off) 0.01 na typ v s = +2.25 v/?.25 v, v d = ?.25 v/+2.25 v; 0.1 0.75 na max test circuit 3 channel on leakage i d , i s ( on) 0.01 na typ v s = v d = +2.25 v/?.25 v; test circuit 4 0.1 0.75 na max digital inputs input high voltage, v inh 1.7 v min input low voltage, v inl 0.7 v max input current i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 2 pf typ dynamic characteristics 2 t transition 14 ns typ r l = 300 ? , c l = 35 pf; test circuit 5 25 ns max v s = 1.5 v/0 v; test circuit 5 break-before-make time delay, t d 8 ns typ r l = 300 ? , c l = 35 pf 1 ns min v s = 1.5 v; test circuit 6 t on (en) 14 ns typ r l = 300 ? , c l = 35 pf 25 ns max v s = 1.5 v; test circuit 7 t off (en) 8 ns typ r l = 300 ? , c l = 35 pf 15 ns max v s = 1.5 v; test circuit 7 charge injection 3pc typ v s = 0 v, r s = 0 ? , c l = 1 nf; test circuit 8 off isolation ?0 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz ?0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 9 channel-to-channel crosstalk ?0 db typ r l = 50 ? , c l = 5 pf, f = 10 mhz ?0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; test circuit 10 ? db bandwidth 55 mhz typ r l = 50 ? , c l = 5 pf; test circuit 11 c s (off) 13 pf typ f = 1 mhz c d (off) adg758 85 pf typ f = 1 mhz adg759 42 pf typ f = 1 mhz c d , c s (on) adg758 96 pf typ f = 1 mhz adg759 48 pf typ f = 1 mhz power requirements v dd = +2.75 v i dd 0.001 a typ digital inputs = 0 v or 2.75 v 1.0 a max i ss 0.001 a typ v ss = ?.75 v 1.0 a max digital inputs = 0 v or 2.75 v notes 1 temperature range is as follows: b version: ?0 c to +85 c. 2 guaranteed by design, not subject to production test. speci?ations subject to change without notice. (v dd = +2.5 v 10%, v ss = ?.5 v 10%, gnd = 0 v, unless otherwise noted.) b
adg758/adg759 rev. b | page 5 absolute maximum ratings t a = 25? c, unless otherwise noted. parameter rating v dd to v ss 7 v v dd to gnd C0.3 v to +7 v v ss to gnd +0.3 v to C3.5 v analog inputs 1 v ss C 0.3 v to v dd +0.3 v or 30 ma, whichever occurs first digital inputs 1 C0.3 v to v dd +0.3 v or 30 ma, whichever occurs first peak current, s or d 100 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d 30 ma operating temperature range industrial (b version) C40c to +85c storage temperature range C65c to +150c junction temperature 150c chip scale package, ja thermal impedance 32c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 overvoltages at en, a, s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. table i. adg758 truth table a2 a1 a0 en switch condition x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 x = dont care table ii. adg759 truth table a1 a0 en on switch pair x x 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 x = dont care pin configurations 02371-102 14 13 12 1 3 4 v dd 15 gnd s5 s6 11 s7 en s1 2 v ss s2 5 s3 7 d 6 s 4 8 n c 9 n c 1 0 s 8 1 9 a 0 2 0 n c 1 8 a 1 1 7 a 2 1 6 n c adg758 top view (not to scale) notes 1. nc = no connect. 2. exposed pad tied to substrate, v ss . 02371-103 14 13 12 1 3 4 v dd 15 gnd s1b s2b 11 s3b en s1a 2 v ss s2a 5 s3a 7 d a 6 s 4 a 8 n c 9 d b 1 0 s 4 b 1 9 a 0 2 0 n c 1 8 n c 1 7 a 1 1 6 n c adg759 top view (not to scale) notes 1. nc = no connect. 2. exposed pad tied to substrate, v ss .
adg758/adg759 C6C rev. v dd most positive power supply potential v ss most negative power supply in a dual-supply application. in single-supply applications, this should be tied to ground at the device. gnd ground (0 v) reference s source terminal. may be an input or output. dd rain terminal. may be an input or output. in logic control input r on ohmic resistance between d and s r flat(on) flatness is de?ed as the difference between the maximum and minimum value of on resistance as measured over the speci?d analog signal range. i s (off) source leakage current with the switch off i d (off) drain leakage current with the switch off i d , i s (on) channel leakage current with the switch on v d (v s )a nalog voltage on terminals d, s c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured w ith reference to ground. c d , c s (on) on switch capacitance. measured with reference to ground. c in digital input capacitance t transition delay time measured between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t on (en) delay time between the 50% and 90% points of the en digital input and the switch on condition. t off (en) delay time between the 50% and 90% points of the en digital input and the switch off condition. t open off time measured between the 80% points of both switches when switching from one a ddress state to another. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. charge a measure of the glitch impulse transferred from the digital input to the analog output during switching. injection on response the frequency response of the on switch. on loss the loss due to the on resistance of the switch v inl maximum input voltage for logic ? v inh minimum input voltage for logic ? i inl (i inh ) input current of the digital input i dd positive supply current i ss negative supply current terminology b
adg758/adg759 C7C rev. t ypical performance characteristics v d , v s , drain or source voltage ?v 8 01 2345 t a = 25c v ss = 0v 7 6 5 4 3 2 1 0 on resistance ? v dd = 2.7v v dd = 3.3v v dd = 4.5v v dd = 5.5v tpc 1. on resistance as a function of v d (v s ) for single supply v d or v s ?drain or source voltage ?v 8 ?.0 t a = 25c 7 6 5 4 3 2 0 on resistance ? ?.5 ?.0 ?.5 ?.0 ?.5 1.0 1.5 2.0 2.5 3.0 0.5 0 v dd = +2.25v v ss = ?.25v v dd = +2.75v v ss = ?.75v 1 tpc 2. on resistance as a function of v d (v s ) for dual supply v d or v s ?drain or source voltage ?v 0123 45 7 6 5 4 3 2 1 0 on resistance ? +85c +25c ?0c 8 v dd = 5v v ss = 0v tpc 3. on resistance as a function of v d (v s ) for different temperatures, single supply v d or v s ?drain or source voltage ?v 0 0.5 7 6 5 4 3 2 1 0 on resistance ? 1.0 1.5 2.0 2.5 3.0 ?0c +25c +85c 8 v dd = 3v v ss = 0v tpc 4. on resistance as a function of v d (v s ) for different temperatures, single supply v d or v s ?drain or source voltage ?v 7 6 5 4 3 2 1 0 on resistance ? ?.0 ?.5 ?.0 ?.5 ?.0 1.0 1.5 2.0 2.5 0.50 v dd = +2.5v v ss = ?.5v +85c +25c ?0c 3.0 8 ?.5 tpc 5. on resistance as a function of v d (v s ) for different temperatures, dual supply v s , (v d = v dd ?v s ) ?v 01 0.12 current ?na 2345 v dd = 5v v ss = 0v t a = 25c 0.08 0.04 0.00 ?.04 ?.08 ?.12 i d (on), v s = v d i s (off) i d (off) tpc 6. leakage currents as a function of v d (v s ) b
adg758/adg759 C8C rev. 0 0.5 0.12 current ?na 1.0 1.5 2.0 3.0 v dd = 3v v ss = 0v t a = 25c 0.08 0.04 0.00 ?.04 ?.08 ?.12 2.5 i s (off) i d (off) v s , (v d = v dd ?v s ) ?v i d (on), v s = v d tpc 7. leakage currents as a function of v d (v s ) ?.0 0.12 current ?na v dd = +2.5v v ss = ?.5v t a = 25c 0.08 0.04 0.00 ?.04 ?.08 ?.12 ?.5 ?.0 ?.5 ?.0 0 0.5 1.0 1.5 2.0 2.5 i s (off) i d (off) ?.5 3.0 v s , (v d = v dd ?v s ) ?v i d (on), v s = v d tpc 8. leakage currents as a function of v d (v s ) temperature ?c 15 current ?na v dd = 5v, v ss = 0v v dd = +2.5v, v ss = ?.5v ?.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 25 35 45 55 65 75 85 i d (on) i s (off) i d (off) tpc 9. leakage currents as a function of temperature temperature ?c 15 current ?na v dd = 3v v ss = 0v ?.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 25 35 45 55 65 75 85 i d (on) i s (off) i d (off) tpc 10. leakage currents as a function of temperature frequency ?hz 10m 10 current ?a 1m 100 10 1 100n 10n 1n 100 1k 10k 100k 1m 10m t a = 25 c v dd = +2.5v v ss = ?.5v v dd = +3v v dd = +5v tpc 11. supply current vs. input switching frequency frequency ?hz 0 30k attenuation ?db ?0 ?0 ?0 ?0 ?00 ?20 100k 1m 10m 100m v dd = 5v t a = 25c tpc 12. off isolation vs. frequency b
adg758/adg759 C9C rev. frequency ?hz 0 30k attenuation ?db ?0 ?0 ?0 ?0 ?00 ?20 100k 1m 10m 100m v dd = 5v t a = 25c tpc 13. crosstalk vs. frequency frequency ?hz 0 30k attenuation ?db ? 100k 1m 10m 100m ?0 ?5 ?0 v dd = 5v t a = 25c tpc 14. on response vs. frequency voltage ?v ? ? 20 q inj ?pc ? 1 2 5 t a = 25c 10 0 ?0 ?0 ?0 3 ?0 04 v dd = 3v v ss = 0v v dd = +2.5v v ss = ?.5v v dd = 5v v ss = 0v tpc 15. charge injection vs. source voltage b
adg758/adg759 C10C rev. t est circuits r on = v 1 /i ds v s v1 i ds d s test circuit 1. on resistance v d a 0.8v d i s (off) v ss v dd v ss v dd s1 s2 s8 en gnd v s test circuit 2. i s (off) v s a 0.8v d i d (off) v ss v dd v ss v dd s1 s2 s8 en gnd v d test circuit 3. i d (off) a 2.4v d i d (on) v ss v dd v ss v dd s1 s8 en gnd v d nc nc nc = no connect test circuit 4. i d (on) v s8 3v 50% t transition 90% 90% address drive (v in ) 50% 0v v s1 v out t transition a2 d *similar connection for adg759 a1 a0 en gnd adg758 * s1 s8 s2 thru s7 v in 2.4v 50 35pf v dd v ss v dd v ss v s1 v s8 300 r l c l v out test circuit 5. switching time of multiplexer, t transition t open 3v 80% 80% address drive (v in ) 0v v out a2 d *similar connection for adg759 a1 a0 en gnd adg758 * s1 s8 s2 thru s7 v in 2.4v 50 35pf v dd v ss v dd v ss v s 300 r l c l v out test circuit 6. break-before-make delay, t open b
adg758/adg759 C11C rev. output 3v 50% enable drive (v in ) 50% 0v v 0 t on (en) 0v 0.9v 0 0.9v 0 t off (en) a2 d *similar connection for adg759 a1 a0 en gnd adg758* s1 s2 thru s8 v in 35pf v dd v ss v dd v ss v s 300 r l c l v out 50 test circuit 7. enable delay, t on (en), t off (en) logic input (v in ) 3v 0v v out q inj = c l v out v out a2 v out v dd d a1 a0 en gnd adg758 * c l 1nf v dd s v in r s v ss v ss v s *similar connection for adg759 test circuit 8. charge injection v s v out 50 network analyzer r l 50 gnd s d v s off isolation = 20 log v out 0.1f v dd a2 a1 a0 en 2.4v 0.1f v ss v dd v ss 50 test circuit 9. off isolation * similar connection for adg759 channel-to-channel crosstalk = 20 log v out v s a2 d a1 a0 en gnd adg758 * s1 s2 s8 2.4v network analyzer network analyzer r l 50 v out v dd 0.1f v ss 0.1f v dd v ss 50 v s 50 test circuit 10. channel-to-channel crosstalk v s v out 50 network analyzer r l 50 gnd s d v out with switch v out without switch insertion loss = 20 log 0.1f v dd a2 a1 a0 en 2.4v 0.1f v ss v dd v ss test circuit 11. bandwidth power-supply sequencing when using cmos devices, care must be taken to ensure correct power-supply sequencing. incorrect power-supply sequencing can result in the device being subjected to stresses beyond the maximum ratings listed in the data sheet. digital and analog inputs should always be applied after power supplies and ground. for single-supply operation, v ss should be tied to gnd as close to the device as possible. b
adg758/adg759 rev. b | page 12 outline dimensions 20-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg758bcpz C40c to +85c 20-lead lead frame chip scale package (lfcsp_wq) cp-20-6 adg758bcpz-reel7 C40c to +85c 20-lead lead frame chip scale package (lfcsp_wq) cp-20-6 ADG759BCPZ C40c to +85c 20-lead lead frame chip scale package (lfcsp_wq) cp-20-6 ADG759BCPZ-reel C40c to +85c 20-lead lead frame chip scale package (lfcsp_wq) cp-20-6 ADG759BCPZ-reel7 C40c to +85c 20-lead lead frame chip scale package (lfcsp_wq) cp-20-6 1 z = rohs compliant part. revision history 3/13rev. a to rev. b updated outline dimensions ........................................................ 12 changes to ordering guide ........................................................... 12 5/02rev. 0 to rev. a edits to general description section .............................................. 1 updated outline drawings ............................................................ 12 0.50 bsc 0.65 0.60 0.55 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd-1. bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 2.30 2.10 sq 2.00 for proper connection of the exposed pad, refer to the pin configurations section of this data sheet. 1 20 6 10 11 15 16 5 08-16-2010-b ?2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02371-0-3/13(b)

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